- Bachelor's degree
- Master's degree
Description
Responsibilities
Writing block level/micro-architect specifications of modules
RTL coding of modules
Verification of sub-systems using variety of tools and methodologies
Essential Criteria:
Requirements
Essential Criteria:
a minimum 2.1 Honours degree or higher in electronics or computer science (with preference given to MENG)
SystemVerilog, Verilog or VHDL (at least one of these), python(optional)
Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
Able to travel to customer sites and other CEVA sites
Desirable Criteria:
Experience in RTL or GTL design flow with tools such as Synopsys, Cadence, ModelSim, etc